China pushes for 70% homegrown silicon wafer use as domestic firm ramps up 12-inch production — government seeking to localize critical chip supply chain amid AI boom and export restrictions

China is targeting 70% local wafer sourcing as firms like Eswin scale 12-inch production, aiming to reduce reliance on foreign suppliers and support growing AI chip demand.

ASML’s roadmap for chipmaking lithography tools examined — from DUV to Low-NA, High-NA, Hyper-NA, and beyond

ASML shipped 48 EUV lithography systems and 131 immersion DUV tools in 2025, generating €32.7 billion in total revenue and ending the year with a €38.8 billion order backlog.

Intel details 18A-P process node, touts higher performance, lower power, and better thermals — 9% more performance, thermal conductivity improved by 50%

Intel details improvements of 18A-P that include higher performance, lower power, reduced variability, improved yields, and more.

1X Kicks Off Full-Scale Production Of Humanoid Robot Neo

Are we nearing the tipping point for humanoid robots? We actually might, given that 1X just hit full-scale manufacturing of Neo.

Inside Google’s TPU V8 strategy, delivering two chips for two crucial tasks at incredible scale — network scales up to 1 million TPUs per cluster, an advantage over Nvidia AI accelerators

Google announced its eighth-gen TPUs at Cloud Next, shipping two distinct chip designs for the first time in the TPU program’s decade-long history.

Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute

Bolt Graphics has announced its completed tape-out of a test chip for its Zeus GPU, marking the startup’s first move from FPGA emulation to manufactured silicon.

TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027

TSMC strengthens its bifurcated process technology development approach with A14, A13, and N2U aimed at client applications and A16, A12, and N2X for high-performance data center designs.