
SP6 will draw on what the companies described as Intel’s expertise in disaggregated semiconductor design and advanced packaging.

TSMC reportedly intends to increase prices of wafers it processes citing demand, rising costs, and increased investments in new capacity.

SMIC’s N+3 process technology can achieve transistor density comparable to TSMC’s N6 without using EUV lithography, but it fails to deliver performance or efficiency of modern production nodes.

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ASML says that the increased productivity of its Low-NA EUV tools gives it an option to increase the prices of these scanners in the future. The move may have a drastic effect on TSMC’s future expansion plans, as the foundry made a big bet on existing lithography systems.

TSMC’s A14 process technology progresses faster than N2 at this stage of development as developers of both client and AI/HPC plan to use it.

ASML’s comments point to intentions to increase prices, though the company is expected to maintain its value-based approach to price setting. Yet, TSMC is reportedly unhappy about the potential plan.